Hysteresis is an effective technique for enhancing the noise immunity of a logic circuit. High-speed switching circuits, where the switching speed is very high and input swing is very low are especially sensitive to noise. In such applications a precisely defined hysteresis voltage plays an important role in minimizing the effect of glitch signals. Different technologies supports different voltages i.e. the operating voltages and definition of the lower limit of threshold high (VIHmin) and upper limit of low (VILmax) level voltage varies with the technology used.
FIG. 1 shows the value of VIHmin and VILmax for GTL, GTL+, HSTL, SSTL, LVPECL, LVDS or AGP technologies. As is apparent from the figure these technologies support different hysteresis voltage levels (VIHmin−VILmax) e.g., for HSTL, VIHmin is 0.85V while VILmax is 0.65V for a reference voltage of 0.75V yielding a maximum hysteresis voltage of 200 mV around the reference voltage. On the other hand, GTL technology has VIHmin=0.85V and VILmax=0.75V for a reference voltage of 0.8V and can thus accommodate a hysteresis voltage of only 100 mV around 0.8 V. Similarly, other standards require different hysteresis values.
It is desired that an integrated circuit should support all available technologies specially when the circuit is expected to have a varying interface. For such cases the IOBs of the integrated circuit need to provide a control mechanism for adjusting the hysteresis according to requirements.
FIG. 2 is the simplified circuit diagram of an IOB in accordance with U.S. Pat. No. 5,958,026. This IOB can support the HSTL, GTL, GTL+IO standards which have a reference voltage VREF below 0.7V. The circuit operates as comparator whose trip voltage is set at VREF and whenever the signal crosses VREF the output changes. These type of IOBs do not provide any hysteresis option and hence a small amount of noise in the inputs can result in a false output.
FIG. 3 shows a similar IOB using inverted logic. The operation of this IOB is similar to that of FIG. 2. This IOB can support SSTL2, SSTL3 and LVPECL IO standards without hysteresis.
FIG. 4 shows an input receiver used for GTL according to U.S. Pat. No. 5,666,068. This circuit is basically a PMOS differential amplifier having two reference voltages Vin1 and Vin2. Transistors P3 and P4 are the input transistors while transistors P8 and P9 coupled in parallel with P3 and P4, respectively, are used to provide hysteresis. This circuit provides a hysteresis value that is capable of satisfying the GTL standard only. Further, though the hysteresis voltage can be changed by varying the reference voltages Vin1 and Vin2, this is not practically feasible since the sizes of the transistors are fixed in a circuit Therefore this circuit does not provide the flexibility to support different technologies.
What is desired, therefore, is a need to develop a system and method that provides a programmable hysteresis voltage to support different technology standards.